Method and apparatus for monitoring a data eye in a clock and data recovery system

ABSTRACT

Methods and apparatus are provided for monitoring a data eye associated with a received signal. A plurality of samples of the received signal are obtained for each unit interval based on a clock recovered from the received signal, to obtain an estimate of the data eye. According to one aspect of the invention, the samples are obtained substantially simultaneous to a decoding of the received signal. The collected data eye samples can optionally be processed, for example, to collect statistics on the received signal or to determine a distribution of the received signal.

FIELD OF THE INVENTION

The present invention is related to techniques for clock and datarecovery (CDR) techniques and, more particularly, to techniques forevaluating a data eye quality in a CDR system.

BACKGROUND OF THE INVENTION

In many applications, including digital communications, clock and datarecovery (CDR) must be performed before data can be decoded. Generally,in a digital clock recovery system, a reference clock signal of a givenfrequency is generated together with a number of different clock signalshaving the same frequency but with different phases. In one typicalimplementation, the different clock signals are generated by applyingthe reference clock signal to a delay network. Thereafter, one or moreof the clock signals are compared to the phase and frequency of anincoming data stream and one or more of the clock signals are selectedfor data recovery.

A number of existing digital CDR circuits use voltage controlled delayloops (VCDL) to generate a number of clocks having the same frequencyand different phase for data sampling (i.e., oversampling). For example,published International Patent Application No. WO 97/14214, discloses acompensated delay locked loop timing vernier. Generally, the disclosedtiming vernier produces a set of timing signals of similar frequency andevenly distributed phase. An input reference clock signal is passedthrough a succession of delay stages. A separate timing signal isproduced at the output of each delay stage. The reference clock signaland the timing signal output of the last delay stage are compared by ananalog phase lock controller. The analog phase lock controller controlsthe delay of all stages so that the timing signal output of the laststage is phase locked to the reference clock. Based on the results ofthe oversampled data, the internal clock is delayed so that it providesdata sampling adjusted to the center of the “eye.” The phase of the VCDLis adjusted to keep up with phase deviations of the incoming data.

FIG. 1 illustrates the transitions in a data stream 100. As shown inFIG. 1, the data is ideally sampled in the middle between two transitionpoints. The phases generated by the VCDL are adjusted to align with thetransitions and sample points, respectively. Thus, the internal clock isdelayed so that the data sampling is adjusted to the center of the“eye,” in a known manner.

In many CDR applications, it is important to monitor the data eye at theinput to a CDR channel. A number of techniques have been proposed orsuggested for data eye monitoring that rely on an external oscilloscopepositioned at the receiver input. The connection of an externaloscilloscope in such a manner, however, loads the input and therebydisturbs the data integrity and alters the results (especially at highdata rates). Another approach employs high speed undersamplinganalog-to-digital (A/D) conversion inside the receiver channel. Suchundersampled A/D conversion, however, requires significant area andpower, as well as an asynchronous input to sweep the input eye. Inaddition, such conventional techniques must be performed off-line (i.e.,conventional techniques cannot simultaneously monitor the data eye andperform clock recovery for data decoding) and are asynchronousapproaches (i.e., are not based on the recovered clock).

A need therefore exists for improved techniques for monitoring a dataeye in a CDR system that can operate online, while the CDR system isoperating. A further need exists for improved techniques for monitoringa data eye in a CDR system that are synchronized to the recovered clock.

SUMMARY OF THE INVENTION

Generally, methods and apparatus are provided for monitoring a data eyeassociated with a received signal. A plurality of samples of thereceived signal are obtained for each unit interval based on a clockrecovered from the received signal, to obtain an estimate of the dataeye. According to one aspect of the invention, the samples are obtainedsubstantially simultaneous to a decoding of the received signal. Thecollected data eye samples can optionally be processed, for example, tocollect statistics on the received signal or to determine a distributionof the received signal.

In one embodiment, a plurality of latches are employed to obtain theplurality of samples, and a value of the received signal is estimated bycomparing values of two or more latches. The plurality of latches samplethe received signal by sampling said received signal for N steps withina unit interval, and for M voltage levels. In another embodiment, asample and hold circuit is employed to obtain a plurality of values ofthe received signal. In addition, an analog-to-digital converteroptionally converts an output of the sample and hold circuit to adigital value.

A more complete understanding of the present invention, as well asfurther features and advantages of the present invention, will beobtained by reference to the following detailed description anddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates the transitions in a data stream, often referred toas a “data eye;”

FIG. 2 is a schematic block diagram illustrating a data eye qualitymonitoring system 200 incorporating features of the present invention;

FIG. 3 illustrates an exemplary VCDL incorporating features of thepresent invention;

FIG. 4 illustrates the relationship between the various phase outputs ofthe VCDL of FIG. 3 to the data eye of FIG. 1;

FIG. 5 illustrates the monitoring of the output of the VCDL of FIG. 3 inaccordance with one embodiment of the present invention;

FIG. 6 illustrates the sampling of the data eye by the roaming latchesof FIG. 4 in further detail;

FIG. 7 is a schematic block diagram illustrating a control system formonitoring of the VCDL output by the roaming latches of FIG. 4;

FIG. 8 is a schematic block diagram illustrating one exemplaryimplementation of a data eye monitoring system incorporating features ofthe present invention;

FIG. 9 is a schematic block diagram illustrating an alternateimplementation of a data eye monitoring system that sub-samples the dataeye at a decimated rate; and

FIG. 10 illustrates a series of data eyes that are selectively sampledin accordance with the embodiment of FIG. 9.

DETAILED DESCRIPTION

The present invention provides methods and apparatus for monitoring adata eye in a CDR system.

FIG. 2 is a schematic block diagram illustrating a data eye qualitymonitoring system 200 incorporating features of the present invention.As shown in FIG. 2, a received signal is processed by a clock and datarecovery circuit 210 to generate the decoded data and recovered clock,in a known manner. Generally, the clock and data recovery circuit 210adjusts a clock signal generated by a voltage controlled delay line 220to maintain a phase alignment between the recovered clock and thereceived signal.

According to one aspect of the invention, a data eye quality monitoringsystem 200 is provided that samples the data eye associated with thereceived signal. As discussed hereinafter, the data eye qualitymonitoring system 200 can evaluate the data eye while the clock and datarecovery circuit 210 is operating. In addition, as shown in FIG. 2 anddiscussed further below, the data eye quality monitoring system 200 isclocked using the recovered clock. In one embodiment discussed herein, avariable delay stage 230 can be employed to tune the phase of therecovered clock in order to sample the received signal in the timedomain. Thus, the data eye monitoring is synchronized to the recoveredclock.

FIG. 3 illustrates an exemplary VCDL 300 incorporating features of thepresent invention. The exemplary VCDL 300 employs coarse phase controlusing injection point control, as well as a fine phase control providedby a central interpolator 330. Thus, the PLL signal that is injectedinto the VCDL 300 is first interpolated to provide fine phase control.Following the fine phase control, the injection point may optionally beadjusted to provide a coarse phase control, as further described in U.S.patent application Ser. No. 10/999,889, filed Nov. 30, 2004, entitled,“Voltage Controlled Delay Loop With Central Interpolator,” incorporatedby reference herein.

As shown in FIG. 3, the input PLL signal, for example, having afrequency of 1-3 GHz, is applied to an optional frequency divider 310that reduces the frequency, for example, in half. The output of thecentral interpolator can optionally be injected in any delay stage inthe VCDL loop. The output of the frequency divider 310 is then appliedto a delay stage 320 having one or more delay elements (e.g., eachproviding a ¼ UI delay). The delay stage 320 is connected to the centralinterpolator 330 such that the left and right inputs to the centralinterpolator 330 are separated by at least one delay element, as shownin FIG. 3.

The exemplary central interpolator 330 provides, for example, 8 distinctphases (over ¼ UI range), between each coarse phase setting. Amultiplexer 340 selects the desired phase. If the phase must be adjustedbeyond the granularity provided by the central interpolator 330 (i.e.,more than a ¼ UI), then a coarse phase adjustment is made by adjustingthe injection point (providing a granularity of ¼ UI).

As shown in FIG. 3, the quadrature phase outputs of the VCDL 300 (T0,T1, T2, T3), are applied to an interpolating multiplexer 350 that cangenerate N taps between any two quadrature clocks. The interpolatingmultiplexer 350 comprises first and second multiplexers 360-1 and 360-2that each receive the quadrature phase outputs of the VCDL (T0, T1, T2,T3). Each multiplexer 360-1 and 360-2 selects a desired phase that isinterpolated by an interpolator 370. The output of the interpolator 370is an interpolation clock, Q1, that has a phase that is between thephases of the clocks selected by the multiplexers 260-1 and 260-2, in aknown manner.

FIG. 4 illustrates the relationship between the various phase outputs ofthe VCDL of FIG. 3 to the data eye 100 of FIG. 1, for a full rate clock410 and a half rate clock 420. As used herein, the notation “TEn”indicates an early transition phase n, the notation “TLn” indicates alate transition phase n and the notation “Sn” indicates a sample pointn. In addition, according to the present invention, the data eyeassociated with the received data is sampled. In one exemplaryembodiment, discussed below in conjunction with FIGS. 4 through 8, thedata eye 100 is sampled using a plurality of latches, and the valuessampled by the plurality of latches are compared to infer the locationof the data eye 100. In another embodiment, discussed below inconjunction with FIGS. 9 and 10, the data eye 100 is sampled using asample and hold circuit that measures the data eye directly.

In one exemplary embodiment shown in FIG. 4, a set of three latches(430-top, 430-ctr, 430-btm) are employed to sample the data eye 100.Generally, each latch has a data input, a clock input and an output. Thereceived data (i.e., the data eye) is applied to the data input and theinterpolated clock Q1 from the VCDL 300 is applied as the clock input(see also variable delay 230 in FIG. 2). The set of three latches430-top, 430-ctr, 430-btm can be programmed horizontally to move leftand right with N taps per data eye (for example, by interpolating thephase outputs applied to the clock input of each latch). In this manner,the data eye quality monitoring system 200 is clocked using therecovered clock. Thus, the data eye monitoring is synchronized to therecovered clock.

In addition, the zero cross center latch 430-ctr is always fixed in avertical direction, for example, at the zero cross. The top and bottomroaming latches 430-top, 430-btm can move up and down in a verticaldirection from the zero cross latch 430-ctr by programming a variablethreshold voltage that is applied to the data input of each latch with Mvoltage levels. The output interpolation clock Q1 of FIG. 3 can bedistributed to the roaming latches 430-top, 430-ctr, 430-btm,hereinafter, collectively referred to as roaming latches 430.

FIG. 5 illustrates the monitoring of the output of the VCDL 300 of FIG.3 in accordance with one embodiment of the present invention. As shownin FIG. 5, the roaming three latches 430-top, 430-ctr and 430-btm ofFIG. 4 can be programmed to move horizontally and vertically to provideN×M roaming latch options, with N latch options per data eye having atime orientation (e.g., horizontal) and M latch options per data eyehaving a voltage orientation (e.g., vertical). In this manner, the dataeye value can be sampled over N×M positions within the eye to obtain anaccurate visualization of the data eye 100. In one exemplary embodiment,there are N=64 steps per unit interval (UI) in the horizontal directionand M=128 steps in the vertical direction (64 steps above the zerocrossing and 64 steps below the zero crossing).

FIG. 6 illustrates the sampling of the data eye by the roaming latches430, in further detail. As previously indicated, roaming three latches430-top, 430-ctr, 430-btm can be programmed horizontally to move leftand right with N taps per data eye (for example, by interpolating thephase outputs). In addition, the zero cross center latch 430-ctr isalways fixed in a vertical direction, for example, at the zero cross, asshown in FIG. 6. The top and bottom roaming latches 430-top, 430-btm canmove up and down in a vertical direction from the zero cross latch430-ctr by programming a variable threshold voltage input to each latchwith M voltage levels.

Thus, whether or not the value of the center latch 430-ctr matches thevalue of the top and bottom latches, 430-top, 430-btm, provides anindication of boundaries of the data eye 100. If the center latch430-ctr has the same value as the top latch 430-top, they are said tomatch. Thus, for samples taken inside a data eye, such as the data eye610, it would be expected that the value of the center latch 330-ctrmatches the value of the top and bottom latches, 430-top, 430-btm. Forsamples taken along the boundary of the data eye, such as the data eye610, it would be expected that some of the values of the center latch430-ctr will match some of the values of the top and bottom latches,430-top, 430-btm. For samples taken outside a data eye, such as the dataeye 610, it would be expected that the value of the center latch 430-ctrwill not match the value of the top and bottom latches, 430-top,430-btm.

FIG. 7 is a schematic block diagram illustrating a control system 700for monitoring of the VCDL output by the roaming latches 430. In oneexemplary implementation, for each of the N horizontal positionsassociated with a given eye, the roaming latches 430 are stepped througheach of the M vertical levels to obtain the data eye samples. For eachposition in the N×M array of sampled locations, the respective values ofthe roaming latches 430 are evaluated for a predefined duration,controlled by a timer 710. In one exemplary implementation discussedfurther below in conjunction with FIG. 8, for each position in the N×Marray of sampled locations, a counter 720 counts the number ofmismatches during the predefined duration between the center latch430-ctr and the top and bottom latches, 430-top, 430-btm. The countmetric generated by the counter 720 is provided, for example, via aserial interface 730 to a computing device 740, such as a personalcomputer or an 8051 microprocessor, for further analysis.

Generally, once the data for the N×M points is loaded into the computingdevice 740, the data can be analyzed and the data eye 100 with intensityinformation, such as a hit rate, can be drawn on the screen. For a givenposition in the N×M array of sampled locations, the hit rate can bedefined, for example, as the number of mismatches during the predefinedduration between the center latch 430-ctr and the top or bottom latch,430-top, 430-btm, associated with the position. For example, if a givenposition is above the zero crossing point, the value of the center latch430-ctr is compared to the value of the top latch, 430-top. In thismanner, the resulting viewable output can be presented withoutdisturbing the data integrity.

FIG. 8 is a schematic block diagram illustrating one exemplaryimplementation of a data eye monitoring system 800 incorporatingfeatures of the present invention. As shown in FIG. 8, the outputs ofthe roaming latches 430 are applied to a pair of exclusive OR (XOR)gates 810, 820, in the manner shown in FIG. 8. A first XOR gate 810compares the value of the center latch 430-ctr to the value of the toplatch 430-top. If the values of the center latch 430-ctr and top latch430-top match, the XOR gate 810 will generate a binary value of 0 and ifthe values of the center latch 430-ctr and top latch 430-top do notmatch, the XOR gate 810 will generate a binary value of 1, in a knownmanner. Thus, a “hit” occurs for points above the zero crossing when thevalues of the center latch 430-ctr and top latch 430-top do not match.

Likewise, a second XOR gate 820 compares the value of the center latch430-ctr to the value of the bottom latch 430-btm. If the values of thecenter latch 430-ctr and bottom latch 430-btm match, the XOR gate 820will generate a binary value of 0 and if the values of the center latch430-ctr and bottom latch 430-btm do not match, the XOR gate 820 willgenerate a binary value of 1, in a known manner. Thus, a “hit” occursfor points below the zero crossing when the values of the center latch430-ctr and bottom latch 430-btm do not match.

As shown in FIG. 8, the exemplary data eye monitoring system 800includes one or more counters 830, 840 for counting the “hit rate” forpoints above and below the zero crossing, respectively. It is noted thata single shared counter 830 can be employed to count the “hit rate” forpoints above and below the zero crossing, as would be apparent to aperson of ordinary skill in the art.

FIG. 9 is a schematic block diagram illustrating an alternateimplementation of a data eye monitoring system 900 that sub-samples thedata eye 100 at a decimated rate. In other words, as shown in FIG. 10,the data eye monitoring system 900 does not sample each data eye 100,but rather every other data eye 1000 is sampled, such as each odd dataeye 1000-1, 1000-3, 1000-5, 1000-7.

In the exemplary embodiment of FIG. 9, the data eye 100 is sampled usinga sample and hold circuit 930 that measures the data eye directly. Asshown in FIG. 9, the received data is applied to the input of the sampleand hold circuit 930. In addition, the clock signal Q1 discussed above,from the VCDL 300, is applied to the clock input of the sample and holdcircuit 930. The various phases of the VCDL 300 are applied to amultiplexer 920 that selects a phase under control of a counter 910. Thesample and hold circuit 930 samples the received data (i.e., the dataeye) and provides a voltage level that is applied to ananalog-to-digital converter 940.

A plurality of identical die are typically formed in a repeated patternon a surface of the wafer. Each die includes a device described herein,and may include other structures or circuits. The individual die are cutor diced from the wafer, then packaged as an integrated circuit. Oneskilled in the art would know how to dice wafers and package die toproduce integrated circuits. Integrated circuits so manufactured areconsidered part of this invention.

It is to be understood that the embodiments and variations shown anddescribed herein are merely illustrative of the principles of thisinvention and that various modifications may be implemented by thoseskilled in the art without departing from the scope and spirit of theinvention.

1. A method for monitoring a data eye associated with a received signal,comprising: obtaining a plurality of samples of said received signal foreach unit interval based on a clock recovered from said received signal.2. The method of claim 1, wherein said obtaining step is performedsubstantially simultaneous to a decoding of said received signal.
 3. Themethod of claim 1, wherein said obtaining step further comprises thesteps of sampling said received signal using a plurality of latches andestimating a value of said received signal by comparing values of saidlatches.
 4. The method of claim 3, wherein said plurality of latchessample said received signal by sampling said received signal for N stepswithin a unit interval.
 5. The method of claim 3, wherein said pluralityof latches sample said received signal by sampling said received signalfor M voltage levels.
 6. The method of claim 3, wherein said pluralityof latches are clocked using said clock recovered from said receivedsignal.
 7. The method of claim 1, wherein said obtaining step furthercomprises the steps of sampling said received signal using a sample andhold circuit to obtain a plurality of values of said received signal. 8.The method of claim 7, further comprising the step of converting anoutput of said sample and hold circuit to a digital value.
 9. The methodof claim 1, further comprising the step of collecting statistics on saidreceived signal.
 10. The method of claim 1, further comprising the stepof determining a distribution of said received signal.
 11. A circuit formonitoring a data eye associated with a received signal, comprising: aplurality of latches for obtaining a plurality of samples of saidreceived signal for each unit interval based on a clock recovered fromsaid received signal.
 12. The data eye monitoring circuit of claim 11,wherein said plurality of latches obtain said plurality of samplessubstantially simultaneous to a decoding of said received signal. 13.The data eye monitoring circuit of claim 11, wherein a value of saidreceived signal is estimated by comparing values of said latches. 14.The data eye monitoring circuit of claim 13, wherein said plurality oflatches sample said received signal by sampling said received signal forN steps within a unit interval.
 15. The data eye monitoring circuit ofclaim 13, wherein said plurality of latches sample said received signalby sampling said received signal for M voltage levels.
 16. The data eyemonitoring circuit of claim 13, wherein said plurality of latches areclocked using said clock recovered from said received signal.
 17. Acircuit for monitoring a data eye associated with a received signal,comprising: a sample and hold circuit for obtaining a plurality ofsamples of said received signal for each unit interval based on a clockrecovered from said received signal.
 18. The data eye monitoring circuitof claim 17, wherein said plurality of samples are obtainedsubstantially simultaneous to a decoding of said received signal. 19.The data eye monitoring circuit of claim 17, further comprising aanalog-to-digital converter to convert an output of said sample and holdcircuit to a digital value.
 20. An integrated circuit, comprising: acircuit for monitoring a data eye associated with a received signal,comprising means for obtaining a plurality of samples of said receivedsignal for each unit interval based on a clock recovered from saidreceived signal.
 21. The integrated circuit of claim 20, wherein saidmeans for obtaining further comprises a plurality of latches and whereina value of said received signal is estimated by comparing values of saidlatches.
 22. The integrated circuit of claim 20, wherein said means forobtaining further comprises a sample and hold circuit to obtain aplurality of values of said received signal.
 23. The integrated circuitof claim 22, further comprising a analog-to-digital converter to convertan output of said sample and hold circuit to a digital value.